Electronic design automation (EDA) software tools are utilized by circuit developers to design and fully test their circuit designs before manufacturing (i.e., fabricating or otherwise producing) physical circuit structures. As used herein, the terms “IC design” and “circuit design” refer to a software-based description of an integrated circuit (IC) from an initial circuit concept (general system level description) to a final transistor-level description. In contrast, the terms “IC/circuit structure” and “IC/circuit device” generally refer to a physical integrated circuit (IC) device that is fabricated on a semiconductor substrate using a layout (technology) file defined by the final (transistor-level description) circuit and a selected semiconductor (e.g., CMOS) fabrication system. Modern EDA software tools typically include a suite of toolsets (tool types) that seamlessly integrate different operations associated with the design/development of a circuit design, such as system and logic design toolsets, synthesis toolsets, toolsets for various types of testing and verification, toolsets for layout and routing, and mask preparation toolsets. Because modern circuits (e.g., System-on-Chip devices) can include billions of transistors and other circuit elements, EDA tools have become essential in the arrangement and interconnection of the multiple circuit types of modern circuit designs. Moreover, because the post-fabrication discovery of design flaws can cause significant production delays and significantly affect profitability of a circuit device, EDA tools have become essential in the pre-fabrication testing/verification of modern circuit designs. That is, without EDA software tools, the efficient generation a modern circuit from concept to physical circuit device would be practically impossible.
Technology Computer-Aided Design (TCAD) tools/toolsets represent one type of EDA test/verification tool that allows circuit designers and device/process/integration engineers to model and simulate physics-based descriptions of specific circuit elements utilized in their circuit designs in order to verify that the operational characteristics of the specific circuit elements are compatible with design constraints. TCAD tools are distinguished from other EDA test/verification tools in that they generate test/verification data by simulating the operation of circuit elements using physics-based 1D, 2D or 3D models of the circuit elements. By way of comparison, functional verification tools are utilized to verify that the overall logic of a circuit design conforms to specifications, and formal verification tools are utilized to prove/disprove the correctness of intended algorithms underlying a circuit design, where neither of these EDA test/verification tool types utilize physics-based operations physics-based 2D or 3D models of circuit elements used in the corresponding circuit design.
TCAD modeling generally involves generating a virtual physics-based representation of a specific circuit element including material characteristics (e.g., type and doping profiles) and feature sizes. For example, a TCAD model may be generated by way a computer-implemented fabrication process in which a selected circuit element is virtually fabricated using associated layout (technology) file information and processing details of a selected fabrication process, thereby providing the model with virtual versions of the various material structures and doped semiconductor regions that would be physically produced if the circuit element was actually fabricated using the layout file and selected fabrication process. An exemplary two-dimensional (2D) TCAD model is described below with reference to FIG. 11B, and an exemplary three-dimensional (3D) TCAD model is described below with reference to FIG. 13B. As described in additional detail below, each TCAD model includes multiple cells (unit elements) that collectively replicate the spatial and compositional characteristics of a corresponding physical circuit element. That is, the multiple cells are arranged in array or matrix such that positional data of the outermost cells corresponds to the spatial boundaries of the corresponding physical circuit element, and each cell includes compositional data that replicates the material contents of a corresponding portion/region of the physical circuit element. As explained in additional detail below, each cell also includes data fields configured to store simulation data (e.g., a field parameter indicating an electric field generated at the cell's location in response to applied stimulus). Those skilled in the art will recognize that the exemplary models are greatly simplified for brevity.
The generation of a simplified 2D model (virtual representation) is described with reference to FIGS. 11A and 11B. FIG. 11A is a cross-section 2D of a standard MOSFET 50 including a polycrystalline silicon (Poly-Si) gate structure 51, a silicon-dioxide (SiO2) gate oxide layer 52 and a silicon substrate 53 including an N-doped source region S and an N-doped drain region D. FIG. 11B is a graphical depiction of a simplified 2D model 60 that may be generate by a TCAD tool to replicate MOSFET (circuit element) 50. To provide a physics-based virtual representation of MOSFET 50, model 60 is generated with an array of 2D cells that represent corresponding physical portions (e.g., square-shaped 2D regions) of MOSFET 50, where each cell includes 2D positional data and material data that characterize the spatial location and composition of its corresponding physical portion (2D region) of MOSFET 50. For example, model 60 is generated such that, for a given cell E1 to virtually represent an associated portion (2D region) R1 located in gate structure 51 of MOSFET 50, cell E1 is generated with positional data X1,Y1 that corresponds with associated portion R1, and includes material data (e.g., N-doped Poly-Si) describing the composition of the gate material that occupies associated portion R1. Similarly, cell E2 of model 60 is generated with positional data X2,Y2 and associated material data (e.g., SiO2) that correspond with associated portion R2 located in gate oxide layer 52, and cell E2 of model 60 includes positional data X3,Y3 and associated material data (e.g., N-doped Si) that correspond with associated portion R3 located in drain region D. Each 2D cell also includes additional parameter data fields (described below).
The generation of a simplified 3D model is described with reference to FIGS. 12A and 12B. FIG. 12A is a perspective 3D view showing a single-fin FinFET 70 including a polycrystalline silicon (Poly-Si) gate structure 71, a silicon or silicon-germanium (SiGe) fin structure including a source region S and an N-doped drain region D separated by a channel region that passes under/through gate structure 71, a gate insulator layer 72 and a substrate 73. FIG. 12B is a graphical depiction of a simplified 3D model 80 that is generated using known techniques to provide a virtual representation of FinFET 70, whereby model 80 includes a matrix of 3D cells that represent corresponding physical portions (e.g., cube-shaped 3D regions) of FinFET 70, where each cell includes 3D positional data and associated material data that define a corresponding volumetric portion/region of FinFET 70. For example, cell E4 of model 80 includes 3D positional data X4,Y4,Z4 and material data (e.g., N-doped Poly-Si) that correspond with associated portion/region R4 located in gate structure 71 of FinFET 70, and cell E5 of model 80 includes positional data X5,Y5,Z5 and associated material data (e.g., SiGe) that correspond with associated portion R5 located in oxide layer 72. Each 3D cell also includes additional parameter data fields (described below).
TCAD simulation is typically divided into two simulation types: process simulation and device simulation. TCAD process simulation involves simulating various processes (e.g., etching, deposition, oxidation, nitridation, silicidation, epitaxial growth, dopant implantation diffusion, activation, and clustering) that are performed during the fabrication of a given circuit device using a selected fabrication process and an associated layout file information. In contrast, TCAD device simulation involves simulating charge carrier (i.e., electrons, holes and sometimes ions) transport through an already-formed TCAD model. Because the primary thrust of the present invention pertains to TCAD device simulation, additional detail regarding TCAD process simulation are omitted herein for brevity, and all subsequent references to TCAD simulation are understood to mean TCAD device simulation unless otherwise specified.
TCAD (device) simulation generally involves virtually subjecting a TCAD model to various simulated operational and environmental conditions that will be applied to the corresponding physical circuit element (e.g., various simulated gate/drain/source voltage levels and various simulated operating temperatures), and then determining and analyzing the model's performance (e.g., the flow of charge carriers) under the simulated conditions. As mentioned above, the goal of TCAD simulation is physics-based replication of the operational characteristics occurring in the corresponding physical circuit element when subjected to actual operational and environmental conditions. In general, the actual operational characteristics of all physical circuit elements (e.g., charge carrier mobility, saturation velocity, impact ionization rate, tunneling currents, etc.) are dependent on quantifiable physical characteristics, whereby these physical characteristics may be quantified using associated parameters. For example, the crystal lattice temperature of a given physical circuit element portion/region during actual operation may be quantified using a corresponding parameter T. Similarly, charge carrier concentrations in the given region may be quantified using parameters n and p, doping concentration may be quantified using parameters Nd and Na, and an applied electric field may be quantified using a parameter F. All of these characteristics/parameters (T, n, p, Nd, Na, F) may be spatially distributed across the physical domain occupied by a given physical circuit element (i.e., the value of each characteristic/parameter may be different in different portions/locations within the volume occupied by a circuit element). Accordingly, each cell of a TCAD model includes a corresponding set of parameters (T, n, p, Nd, Na, F) that quantify corresponding localized characteristics occurring at the cell's location during TCAD simulation. For example, referring to 2D model 60 (FIG. 11B), current through MOSFET 50 (FIG. 11A) in a turned-on operating condition may be estimated by applying a virtual gate voltage to cell E1 while maintaining a suitable virtual drain voltage on cell E3, and then calculating the resulting charge carrier concentration parameters p and n in one or more cells associated with circuit device portions located in source region S. In other words, TCAD simulation involves performing computer-implemented numerical method techniques that calculate cause/effect-type, physics-based changes in the parameters of selected cells in response to the simulated conditions, whereby the TCAD model's simulated reactions to the applied simulated conditions approximate actual reactions of the corresponding physical circuit elements. By facilitating physics-based analysis of different circuit element types and sizes (i.e., by way of simulating the operations of different TCAD models describing the different types/sizes), TCAD tools allow circuit designers to identify specific circuit element configurations that are optimized for a given circuit design.
Modern TCAD tools typically provide various options that allow users to maximize simulation result accuracy at the cost of a longer processing time (i.e., the total time required for a given TCAD model to generate/converge on a solution), or to minimize processing time at the cost of lower result accuracy. As illustrated by 2D model 60 (FIG. 11B), one such option is the ability to perform 2D simulation on a cross-sectional “slice” of a given 3D model, which minimizes a given TCAD model's processing time of by way of reducing the number of simulated cells, but does not provide the result accuracy that would be provided by performing 3D simulation using the entire 3D model. Another option is the ability to define models using different cell resolutions, with a high-resolution model (e.g., one atom per cell) providing more accurate results but requiring substantially more processing time than that required for a corresponding low-resolution model (e.g., 10,000 atoms per cell). Ideally, a circuit designer chooses options that provide sufficiently accurate simulation results while minimizing processing time.
A third option provided by some TCAD tools for reducing processing time in exchange for simulation result accuracy is the option of using either local model simulation techniques (aka, local models) or non-local model simulation techniques (aka, non-local models). Local and non-local model simulation techniques are similar in that both involve computer-implemented formulas that are selectively utilized during TCAD simulation to determine a corresponding physical operational characteristic (e.g., charge carrier tunneling probability) at a given space-point location (e.g., occurring in a selected TCAD model cell). Local and non-local model simulation techniques differ in that local model simulation techniques only utilize operational characteristics (parameter values) at a given space-point location (e.g., occurring in a selected TCAD model cell) to calculate the desired physical operational characteristic. For example, referring to FIG. 13B, a 2D local model simulation technique may utilize only parameter data V22 of a selected TCAD model cell E22 to calculate a charge carrier tunneling probability at the space-point location of cell E22. In contrast, non-local model simulation techniques utilize operational characteristics/parameters simultaneously occurring in multiple space-point locations (e.g., using parameter values stored in the given cell and one or more neighboring cells) to calculate the desired physical operational characteristic. For example, referring to FIG. 13B, an exemplary 2D non-local model simulation technique for determining an electron tunneling probability at cell E22 may depend on an integral of electric field parameter values V31. Similarly, referring to 3D model 90 shown in FIGS. 14A and 14B, a 3D local model simulation technique typically utilizes parameters stored in conjunction with a selected cell E6, whereas a non-local model simulation technique may be determined by associated forces generated in any of the twenty-six adjacent cells surrounding selected cell E6 (or any cells located outside of these adjacent cells). By limiting data processing associated with local model simulation techniques to only the parameter data of the selected cell, local modeling simulation techniques can be performed using a relatively small number of calculations that require relatively a short amount of processing time, and typically achieve convergence on a solution. However, although local modeling simulation techniques may provide sufficiently accurate data for some physical operational characteristics of some circuit elements, the results are typically too inaccurate for analyzing nanodevices and other low-voltage circuit cells produced using cutting-edge processing technologies. That is, as the supply voltages cannot be scaled accordingly without jeopardizing the circuit performance, increased electric fields inside the nanodevices generate large electric field changes, which produce non-local and hot-carrier effects that can dominate nanodevice performance. In contrast, non-local modeling techniques account for these non-local and hot-carrier effects by way of calculating both ‘local’ and ‘non-local’ driving forces, and therefore provide higher accuracy, but require substantially longer processing times than local modeling techniques, and sometimes fail to converge on a solution.
Tunneling leakage is a circuit element operational characteristic that has commanded increased attention as semiconductor processing technologies moves toward nanodevices and other circuit elements having increasingly smaller feature sizes and lower operating voltages. Referring to FIG. 15, tunneling leakage refers to the gradual transfer of electrical energy in the form of charge carriers (e.g., electrons or holes) across a boundary normally viewed as insulating, such as the small but undesirable gate-to-drain current generated in turned-off transistors, where tunneling current increases when the forward voltage exceeds the valence band edge Ev or when the reverse voltage exceeds the conductance band edge Ec. Tunneling leakage was typically considered insignificant in early circuit elements produced using older technologies (e.g., CMOS MOSFETs) because the dielectric materials (e.g., silicon dioxide) used in these circuit elements produced relatively wide bandgaps for the applied operating voltages and feature sizes. As semiconductor processing evolved to provide circuit elements with smaller features sizes and lower operating voltages, the relevance of tunneling leakage began to increase due to higher source/drain doping concentrations. The relevance of tunneling leakage further increased with the recent development of various nanodevices (e.g., FinFETs, nanowires and 2D material transistors having nanometer-scale feature sizes), which are fabricated using cutting-edge semiconductor processing technologies that utilize lower bandgap materials such as SiGe.
As with other simulation measurements, conventional TCAD tools typically include both local modeling BBT measurement techniques and non-local modeling BBT measurement techniques. The non-local modeling techniques include dynamic non-local path band-to-band models that account for the non-local generation of electrons and holes caused by direct and phonon-assisted tunneling processes. As with other non-local measurements, a benefit associated with conventional non-local BBT measurement techniques is that they provide tunneling leakage estimates that match well with actual measurements. However, non-local BBT measurement model require a long time to reach a solution (i.e., converge), and fail to converge about 30% of the time, which may be attributed to the complexity of the equations that need to be solved. That is, non-local BBT simulation models utilize partial differential equations that describe electron and hole transport in the modeled semiconductor device, and are solved by discretizing them over a special mesh covering the simulation domain and linearizing them, and then solving the resultant system of linear equations using usual matrix techniques. Non-local BBT measurement models generate resultant matrices that are denser with more non-zero non-diagonal cells than local BBT measurement models, and such denser matrices are more difficult to solve than less dense matrices, and often fail to converge on (achieve) solution.
Most local BBT measurement models utilized in TCAD simulation are based on the Hurkx equations described in “A New Recombination Model For Device Simulation Including Tunneling”, IEEE Transactions on Electron Devices, Volume 39 Issue 2, February 1992, by G. Hurkx, D. Klaassen and M. Knuvers. In this paper the authors present a recombination model which takes into account band-to-band tunneling in reverse-bias and trap-assisted tunneling in both forward and reverse bias. The recombination model describes a total net recombination rate given by the following Equation 1:R=RTRAP+RBBT  (Equation 1)where RTRAP is the contribution of transitions via traps (including the conventional Shockley-Read-Hall recombination mechanism) and RBBT is the band-to-band tunneling contribution. The trap-assisted tunneling effect RTRAP is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7*105 V/cm. Hurkx et al. teach that for dopant concentrations above 5*1017 cm−3 or, equivalently, for breakdown voltages below approximately 5V, the reverse characteristics are dominated by band-to-band tunneling. The present invention addresses only the band-to-band tunneling portion of Equation 1, and therefore the contribution of transitions via traps is omitted from the following discussion. That is, a model suitable for calculating total net recombination rates according to Equation 1 may utilize the approach for determining the trap-assisted tunneling effect Rtrap taught by Hurkx et al. in combination with the present invention set forth below. Other local BBT measurement models utilized in TCAD simulation, such as those based on Schenk's model (see A. Schenk, “Rigorous Theory and Simplified Model of the Band-to-Band Tunneling in Silicon,” Solid-State Electronics, vol. 36, no. 1, pp. 19-34, 1993), have the same problems described below with reference to Hurkx-based local models, and therefore are not discussed in detail herein for brevity.
The Hurkx model for determining band-to-band tunneling contribution RBBT is copied below as Equation 2, and represents a conventional local modeling technique typically utilized to determine local Band-to-Band-Tunneling (BBT) during TCAD device simulation:RBBT=−B·|F|σ·D(F,E,Efn,Efp)·exp(−F0/(|F|))  (Equation 2)where the term F is the applied electric field, F0 is a temperature-dependent bandgap force that is proportional to Eg3/2 where Eg is the bandgap and is given the value 1.9×107 V/cm at room temperature), and B is a temperature-independent pre-factor having a value of 4×1014 cm−1/2·V−5/2. The term D(F,E,Efn,Efp) is utilized to adjust the Hurkx equation for zero and reverse bias in the manner explained below with reference to FIG. 16. In the exponential exp(−F0/(|F|)), the term F0 is proportional to Eg3/2, where Eg is the bandgap, whereby F0 depends on temperature due to the temperature dependence of the bandgap. As currently understood by the inventors, all Hurkx-based local modeling techniques utilized by conventional TCAD tools to estimate BBT currents are based on Hurkx Equation 2.
FIG. 16 is a graph showing exemplary BBT estimates generated by optional conventional local and non-local modeling techniques provided by a conventional TCAD tool for an arbitrary TCAD model, where the solid-line curve indicates characteristic BBT estimates generated by the conventional non-local modeling technique, and the dashed-line curves shows corresponding BBT estimates generated using the optional Hurkx-based local modeling technique. As indicated by the solid-line curve, characteristic BBT current estimates generated by conventional non-local modeling technique produce a zero BBT current level when the reverse bias field F is zero, a relatively sharp increase in BBT current as the reverse bias field F increases from zero to a relatively low value Fa, a somewhat stable region in which BBT current levels remain substantially constant between relative low value Fa and an intermediate reverse bias field value Fb, and then a sharp increase in BBT current as the reverse bias field F increases above intermediate value Fb. As indicated by the two dashed-line curves, characteristic BBT current estimates generated by conventional Hurkx-based local modeling techniques typically deviate significantly from results generated by non-local modeling techniques for reasons explained below.
As understood in the art, BBT current estimates generated by a non-local TCAD modeling techniques are significantly more accurate (i.e., substantially identical to actual physical measurements) than those generated by Hurkx-based local TCAD modeling techniques. Accordingly, the solid-line curve indicating non-local TCAD modeling results in FIG. 16 (and in other figures referenced herein) are assumed to represent BBT currents generated in actual circuit elements when subjected to a range of applied reverse bias field forces, and the deviation of the dashed-line curves from the solid-line curve depicts corresponding relative error amounts inherent in BBT current estimates generated by Hurkx-based local TCAD modeling techniques. Due to the depicted deviation, one might conclude that all TCAD BBT estimates would be performed using non-local modeling techniques. However, as explained above, non-local modeling techniques require substantially longer processing times in comparison to local modeling techniques, and it is understood in the art that the failure rate of conventional TCAD BBT non-local modeling techniques is approximately 30%. Moreover, as indicated by the single-dot-dash line in FIG. 16 (labeled HURKX1 for reasons explained below), Hurkx-based local modeling techniques can provide acceptably accurate estimates for intermediate to high reverse bias field strengths. Accordingly, because local modeling techniques require substantially less processing time than non-local models and reliably converge on a solution, design engineers often utilize the Hurkx-based local modeling option provided by a given TCAD tool to perform various verification functions.
A growing problem associated with TCAD simulation is that conventional Hurkx-based local modeling techniques are not able to estimate BBT currents in nanodevices and other circuit elements fabricated using cutting-edge semiconductor processing technologies. As explained above, the nanometer-scale feature size and low operating voltages of cutting-edge semiconductor fabrication processes result in circuit devices that undergo very low reverse bias fields (e.g., in the range between zero and value Fa in FIG. 16), and the Hurkx Equation 2 (above) requires a change to the value of term D(F,E,Efn,Efp) at these low reverse bias field levels. That is, curve HURKX1 (single-dot-dashed line in FIG. 16) represents BBT current values generated using Hurkx Equation 2 with term D set to a value of positive-one (+1). As indicated in FIG. 16, this D=1 setting causes the resulting BBT current values of curve HURKX1 to map relatively accurately with the solid-line values associated with non-local modeling results. However, a problem with Hurkx Equation 2 is that, when term D is equal to one, curve HURKX1 does not terminate at the zero-current origin at zero reverse bias field values. In order to address this issue, the D term in Hurkx Equation 2 is changed from positive-one to negative-one (−1) at low below reverse bias field values (e.g., below value Fa in FIG. 16), whereby the Hurkx Equation 2 generates estimated BBT current values indicated by curve HURKX2 (double-dot-dash line) in FIG. 16, which are shifted lower from those of curve HURKX 1 consistent with those. That is, changing the value of term D to negative-one at low reverse bias field values causes the Hurkx Equation 2 to produce a zero-current estimate at zero reverse bias field values, and arguably provides sufficiently accurate estimates for very small reverse bias field values. However, as depicted in FIG. 16, the remaining values of curve HURKX2 (including a large portion of the region between zero and reverse bias field value Fa) are significantly different from those generated by the corresponding non-local modeling techniques. That is, while conventional Hurkx-based local modeling techniques arguably remain suitable for TCAD simulations involving circuit elements produced using older processing flows, they are increasing problematic when applied to nanodevices and other circuit elements fabricated using cutting-edge semiconductor processing technologies.
What is needed is a simulation modeling technique that provides improved BBT current estimates (i.e., more accurate in comparison to conventional local modeling techniques) during the TCAD simulation of low-voltage circuit elements (e.g., nanodevices or generated using cutting-edge fabrication processes) that overcomes the deficiencies of the conventional approaches set forth above. What is particularly needed is TCAD simulation modeling technique exhibiting the low-processing-time and reliable convergence characteristics of conventional local modeling techniques, and also provides estimated BBT current data having an accuracy that is closer to that generated by conventional non-local modeling techniques.